D-PAK With Exposed Copper

The D-PAK shown was trimmed to avoid overhanging the edge of the PCB. This has exposed copper. Is this a defect for a class III?

A.J

Expert Panel Responses

Trimming a component must not be attempted. You are out of specs of the IC manufaturer, and the solder pads holding trimmed copper are also compromized.

Guy Shemesh
General Manager
ePiccolo Engineering

Mr. Shemesh has Bsc. in E.E engineering and hands-on experience with electronics (schematics & layout) since 2004. He has designed dozens of multi-layer PCBs, HDI, RF, rigid-flex, etc., and had the honor for design reviewing veteran layout engineers several times as a consultant.

According to IPC-A-610 section 5.2.1 it is an acceptable condition for Class 1, 2 & 3. Be advised that copper will tend to oxidize and it is a good idea to cover/tin those exposed ends.

Edithel Marietti
Senior Manufacturing Engineer
Northrop Grumman

Edithel is a chemical engineer with 20 year experience in manufacturing & process development for electronic contract manufacturers in US as well as some major OEM's. Involved in SMT, Reflow, Wave and other assembly operations entailing conformal coating and robotics.

I’ve listed information from the 610 and 001 IPC documents related to the acceptability of exposed copper on component leads and on non-solderable portions of leads or wires which have been trimmed. This has been an acceptable condition since IPC-S-815 the precursive document to J-STD-001 during the 1980s, so for over 40 years exposed copper has been an acceptable condition provided it does not impact or affect the formation of the solder connections.

Referencing the IPC documents:

Exposed copper is not a reason to reject a product, provided the achieved wetting characteristic of the solder connection area are acceptable. This has been in effect for

IPC-A-610J, section 5.2.1 Soldering Anomalies – Exposed Basis Metal, exposed copper is acceptable, on vertical conductor edges, cut end of conductors and OSP boards.

Section 8.3.13 BTC Component, Page 8-95. “… there are some package configurations that have no toe exposed or do not have a continuous solderable surface on the exposed toe on the exterior of the package,…” is an acceptable condition.

Section 8.3.14 D-Pak, Table 8-17 Note 2, “..Solder wetting is not required on the trimmed edges of a thermal pad that exposes non-wettable vertical surfaces”

IPC-J-STD-001J Requirement for Soldered Electrical and Electronic Assemblies, Section 7.5.16, Note 2, “..Solder wetting is not required on the trimmed edges of a thermal pad that exposes non-wettable vertical surfaces”

Leo Lambert
Vice President, Technical Director
EPTAC Corporation

At EPTAC Corporation, Mr. Lambert oversees content of course offerings, IPC Certification programs and provides customers with expert consultation in electronics manufacturing, including RoHS/WEEE and lead free issues. Leo is also the IPC General Chairman for the Assembly/Joining Process Committee.

Here, the exposed copper on the D-PAK is a defect. Class 3 boards demand the highest reliability, so exposed copper on solderable surfaces is not allowed. However, you can have up to 1% exposed copper for non-solderable areas.

Amit Bahl
Director of Sales and Marketing
Sierra Circuits

Amit Bahl started to work at Sierra Circuits in 2006 where he formed strong relationships with his customers working with them on flex PCBs, HDI, controlled impedance, etc. In 2009, he was promoted Director of Sales and Marketing.

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